Download e-book for iPad: Advances in Computer Systems Architecture: 9th Asia-Pacific by James E. Smith (auth.), Pen-Chung Yew, Jingling Xue (eds.)

By James E. Smith (auth.), Pen-Chung Yew, Jingling Xue (eds.)

ISBN-10: 3540230033

ISBN-13: 9783540230038

ISBN-10: 354030102X

ISBN-13: 9783540301028

On behalf of this system committee, we have been happy to offer this year’s application for ACSAC: Asia-Paci?c computers structure convention. Now in its 9th 12 months, ACSAC keeps to supply a superb discussion board for researchers, educators and practitioners to return to the Asia-Paci?c area to interchange principles at the most recent advancements in computers structure. This yr, the paper submission and evaluate approaches have been semiautomated utilizing the loose model of CyberChair. We acquired 152 submissions, the most important quantity ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ?ve committee individuals for evaluate. all the papers have been reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the assessment method. whilst reviewers claimed insufficient services, extra reviewers have been solicited. finally, we got a complete of 594 studies (3.9 in keeping with paper) from committee participants in addition to 248 coreviewers whose names are said within the court cases. we wish to thank them all for his or her time and e?ort in supplying us with such well timed and high quality reports, a few of them on tremendous brief notice.

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Additional info for Advances in Computer Systems Architecture: 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004. Proceedings

Sample text

We use 100 million references of them to warm up L1 cache and analysis the behavior of the latter 100 million. The L1 sector cache we simulated is mainly configured as below with small varieties: 16KBsize, 64B line size, 16B sector size, 4 way associ- Efficient Victim Mechanism on Sector Cache Organization 23 ate, LRU replacement algorithm and write-back approach. For L2 cache behavior we use a built-in first level cache together with trace generation. We warm up the built-in cache with 1 billion instructions.

Even it is more difficult to correlate the L2 references back with the source or binary, than L1 references. We still ascribe the better VST performance to its property of avoiding be thrashed. As to the workloads, “ammp” and “SAEC” get most significant cache misses reduction here. This behavior is opposite to the L1 behavior. Also the significant block miss reduction can not be observed in this level as the data in appendix shows. Thus we suggest that the extra storage of LVC and SVC benefit more from the general data locality; and VST benefit more from the cache underutilization whether the reference pattern is regular or not.

As the data cache size increases, the loads with replica of bzip2 decreases slightly, while the loads with replica of equake increases slightly. The reason is that replicas can be found in two places: the L1 data cache and the replica victim cache. The number of replicas that can be stored in the L1 increases as the L1 data cache size increases, however, the relative number of replicas that can be stored in the replica victim cache decreases since the size of replica victim cache is fixed. Therefore, the effect of increasing the L1 data cache size on the loads with replica is dependent on these two factors.

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Advances in Computer Systems Architecture: 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004. Proceedings by James E. Smith (auth.), Pen-Chung Yew, Jingling Xue (eds.)


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